A digital delay locked loop is generally formed of a phase detector which detects the phase difference between a system clock and a feedback clock, and causes adjustment of a time delay circuit in the loop which causes the DLL output clock to be adjusted to lock with the system clock. The time delay is generally formed of an adjustable delay line.
Since the delay line is typically adjusted in steps, the finest delay resolution depends on the delay line step increments. In order to hold the locked condition, the delay line is continuously increased and decreased in step increments around a lock point, which results in inherent tracking jitter. In order to decrease the jitter, the delay line has been formed of plural coarse delay elements (CDE), forming a coarse delay line, in series with plural fine delay elements (FDE). After power-up of the circuit, the coarse delay line is adjusted, and once a lock point has almost been determined, the fine delay line is adjusted, which narrows the window around the lock point, to about 25 picoseconds, which represents the nominal amount of jitter in a typical application.
One fine delay line element (FDE) consists of 32 steps×25 picoseconds resulting in a time delay of about 0.8 ns, which approximately equals the time delay of a single stage of the coarse delay line. Once the delay locked loop has stabilized to the lock point, the delay line will automatically compensate for variations in delay caused by changing temperature and voltage conditions, by varying the fine delay line.
The fine delay line is reset to the halfway point after which it begins tracking.
In case of major drift, adjustments in the fine delay line will overrun its end. In that case, another coarse delay element is switched in series or an existing coarse delay element is switched out of the coarse delay line, and at the same time the fine delay line is adjusted to compensate for the coarse delay increase or decrease to provide the same total delay as before. However, now the fine delay line can be used again to compensate changes without immediate danger of overrun.
U.S. Pat. No. 5,544,203 invented by Casasanta et al, and U.S. Pat. No. 5,604,775 each discuss adjustment of a delay locked loop delay line using coarse and fine adjustment. However, none address the problem solved by the present invention, as will be elaborated below.
It is assumed in the prior art that interchanging (switching) the fine delay line steps for a coarse delay element provides an equal exchange of delay. Indeed, any differences between the two appear as jitter of about 300 ps on the DLL output clock. This amount of jitter was considered to be tolerable, given the prior art primary application of single data rate synchronous dynamic random access memories (SDRAMS). However, with the advent of tighter access time (Tac) specifications for double data rate (DDR) SDRAMs which are synchronized to the rising and falling edges of a system clock rather than only to the rising edge, even an amount of jitter of 200 ps-300 ps is becoming intolerable, considering the numerous sources adding to this jitter apart from the DDL, including input clock to data skew, clock duty cycle variations, inaccuracies in the actual input and output buffer delays with respect to its design model, etc.
DLL jitter itself consists of factors such as inherent tracking jitter and supply noise and substrate noise induced jitter. The inherent tracking jitter is caused by the up and down adjustments to the fine delay line while the DLL is in the locked condition, and as described above, is a variation equivalent to the delay achieved through a single step in the delay line. The jitter caused by switching between the coarse and fine delay elements caused by the mismatch between the elements is referred to as a switching jitter. This mismatch is highly dependent on the manufacturing process, and thus is hard to predict in the design stage. As the operating frequencies continue to increase, the switching jitter can undesirably reduce the data eye significantly. In addition, since this switching occurs only infrequently, it is inherently hard to detect during testing and can cause apparently randomly dropped bits when the part is in use in the field.
Analog techniques can be used to achieve a wide range of fine resolution tracking for various applications. In particular DLLs based on phase mixers have been shown to achieve high fine resolution tracking range through quadrature mixing. However, most analog based DLL designs employ some form of charge pumps for voltage controlled delay lines and as such they suffer from a limited resolution of the delay steps since the controlling element affects an entire delay line. In addition such DLLs often require a large acquisition time due to loop bandwidths being limited to a small fraction of the clock frequency to ensure stability of the loop. This effect also causes a poor jitter performance in analog DLLs.
Furthermore, analog DLL designs are inherently more susceptible to all sources of noise as their control variables (usually voltage) are reduced to achieve finer resolutions. In particular, SDRAMs provide a very noisy environment for analog blocks in form of supply and substrate noise, which when combined with area restrictions in SDRAMs, sometimes preventing adequate implementation of noise prevention techniques through layout, can result in unreliable DLLs in noisy field environments.